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<title>SUBPD—Subtract Packed Double-Precision Floating-Point Values </title></head>
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<h1>SUBPD—Subtract Packed Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F 5C /r</p>
<p>SUBPD xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG 5C /r</p>
<p>VSUBPD xmm1,xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Subtract packed double-precision floating-point values in xmm3/mem from xmm2 and store result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG 5C /r</p>
<p>VSUBPD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Subtract packed double-precision floating-point values in ymm3/mem from ymm2 and store result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W1 5C /r</p>
<p>VSUBPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Subtract packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W1 5C /r</p>
<p>VSUBPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Subtract packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W1 5C /r</p>
<p>VSUBPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Subtract packed double-precision floating-point values from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs a SIMD subtract of the two, four or eight packed double-precision floating-point values of the second Source operand from the first Source operand, and stores the packed double-precision floating-point results in the destination operand.</p>
<p>VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corre-sponding destination register are zeroed.</p>
<p>VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corre-sponding destination register are zeroed.</p>
<p>EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM registers. The destination operand is conditionally updated according to the writemask.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding register destination are unmodified.</p>
<p><strong>Operation</strong></p>
<p><strong>VSUBPD (EVEX encoded versions) when src2 operand is a vector register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) SRC1[i+63:i] - SRC2[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSUBPD (EVEX encoded versions) when src2 operand is a memory source</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197) SRC1[i+63:i] - SRC2[63:0];</p>
<p>ELSE</p>
<p>EST[i+63:i] (cid:197) SRC1[i+63:i] - SRC2[i+63:i];</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSUBPD (VEX.256 encoded version)</strong></p>
<p>DEST[63:0] (cid:197) SRC1[63:0] - SRC2[63:0]</p>
<p>DEST[127:64] (cid:197) SRC1[127:64] - SRC2[127:64]</p>
<p>DEST[191:128] (cid:197) SRC1[191:128] - SRC2[191:128]</p>
<p>DEST[255:192] (cid:197) SRC1[255:192] - SRC2[255:192]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VSUBPD (VEX.128 encoded version)</strong></p>
<p>DEST[63:0] (cid:197) SRC1[63:0] - SRC2[63:0]</p>
<p>DEST[127:64] (cid:197) SRC1[127:64] - SRC2[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>SUBPD (128-bit Legacy SSE version)</strong></p>
<p>DEST[63:0] (cid:197) DEST[63:0] - SRC[63:0]</p>
<p>DEST[127:64] (cid:197) DEST[127:64] - SRC[127:64]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSUBPD __m512d _mm512_sub_pd (__m512d a, __m512d b);</p>
<p>VSUBPD __m512d _mm512_mask_sub_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);</p>
<p>VSUBPD __m512d _mm512_maskz_sub_pd (__mmask8 k, __m512d a, __m512d b);</p>
<p>VSUBPD __m512d _mm512_sub_round_pd (__m512d a, __m512d b, int);</p>
<p>VSUBPD __m512d _mm512_mask_sub_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);</p>
<p>VSUBPD __m512d _mm512_maskz_sub_round_pd (__mmask8 k, __m512d a, __m512d b, int);</p>
<p>VSUBPD __m256d _mm256_sub_pd (__m256d a, __m256d b);</p>
<p>VSUBPD __m256d _mm256_mask_sub_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);</p>
<p>VSUBPD __m256d _mm256_maskz_sub_pd (__mmask8 k, __m256d a, __m256d b);</p>
<p>SUBPD __m128d _mm_sub_pd (__m128d a, __m128d b);</p>
<p>VSUBPD __m128d _mm_mask_sub_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);</p>
<p>VSUBPD __m128d _mm_maskz_sub_pd (__mmask8 k, __m128d a, __m128d b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 2.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E2.</td></tr></table></body></html>